1. Field of the Invention
The present invention relates to a field-effect transistor (FET) composed of nitride-based group III-V compound semiconductors, and more particularly relates to a normally-off field-effect transistor.
2. Description of the Background Art
A conventional field-effect transistor employing nitride-based group III-V compound semiconductors includes a GaN layer and an AlGaN layer stacked with each other on a substrate (refer to U.S. Pat. No. 5,192,987). The AlGaN layer has a smaller lattice constant as compared with the GaN layer.
A field-effect transistor employing nitride-based group III-V semiconductors includes a hetero-structure of AlGaN/GaN, for example. In formation of this hetero-structure, a thin AlGaN layer having a thickness of 20 nm, for example, is epitaxially grown on a relatively thick GaN layer having a thickness of 1 μm, for example. The AlGaN layer, having a smaller lattice constant aAlGaN as compared with a lattice constant aGaN of the GaN layer (aGaN>aAlGaN), receives tensile stress from the GaN layer. Interfacial local energy levels formed at the AlGaN/GaN interface on the side of the GaN layer having a relatively small band gap confines piezoelectric charge induced by the tensile stress and charge resulting from spontaneous polarization specific to the nitride semiconductors having a wurtzite structure, thereby automatically generating two-dimensional electron gas.
In other words, even when the gate voltage is zero in the field-effect transistor including the hetero-structure, a region (channel region) where electrons are present is created and then electrons can flow through the channel region. Therefore, such a transistor is referred to as a normally-on transistor.
A graph of FIG. 4 schematically illustrates exemplary static characteristics in such a normally-on FET. In this graph, a horizontal axis represents the source-to-drain voltage VDS, and a vertical axis represents the drain current ID. As seen in FIG. 4, even when the gate voltage Vg is zero, the drain current ID flows upon application of the voltage VDS between a source and a drain.
In consideration of application to a general circuit, a normally-off FET is more preferable, in which the current ID does not flow when the gate voltage Vg is zero. The reason of this is that even when some trouble occurs in the circuit, overcurrent does not flow between the source and drain of the normally-off FET unless the voltage Vg is applied to the gate, and thus there is much less possibility that the semiconductor device including the FET breaks down. If the gate voltage Vg is reduced to zero for some cause in a normally-on FET, on the other hand, overcurrent can flow between the source and drain, and there is a possibility that the transistor itself breaks down.
A MOS (metal-oxide-semiconductor) FET employing Si can be formed as a normally-off FET. When the gate voltage Vg is zero in the MOSFET employing Si, the drain current ID does not flow irrespective of application of the voltage VDS between the source and drain, as seen in a graph of FIG. 5 similar to FIG. 4.
In an n-type MOSFET employing Si, an n-type source region and an n-type drain region are formed at a small interval on a p-type Si substrate. A similar structure is theoretically formable also by using a GaN substrate. In the case of GaN, however, it is not easy to form a high-quality p-type layer and it is very difficult to form an n-type region within a p-type layer by ion implantation or diffusion, dissimilarly to the case of Si. Therefore, a MOSFET including no hetero-structure (e.g., GaN-MOSFET) has not yet been put into practice. While there is a MOSFET including an AlGaN/GaN hetero-structure (i.e., MOS-HFET), this is a normally-on FET.
When a normally-off FET is formed with GaN, a short switching time can be expected due to higher electron mobility in GaN as compared with Si, and power loss of the transistor can be remarkably improved to ⅕ to 1/10, thereby to enable energy saving and downsizing of an electronic device.
As described before, however, it is difficult to prepare a normally-off field-effect transistor including a hetero-structure.